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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5 Monolithic 3A, 1.25MHz Step-Down Switching Regulator
FEATURES
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DESCRIPTIO
3A Switch in a Thermally Enhanced 16-Lead TSSOP or 8-Lead SO Package Constant 1.25MHz Switching Frequency Wide Operating Voltage Range: 3V to 25V High Efficiency 0.09 Switch 1.2V Feedback Reference Voltage Uses Low Profile Surface Mount Components Low Shutdown Current: 15A Synchronizable to 2MHz Current Mode Loop Control Constant Maximum Switch Current Rating at All Duty Cycles*
The LT(R)1765 is a 1.25MHz monolithic buck switching regulator. A high efficiency 3A, 0.09 switch is included on the die together with all the control circuitry required to construct a high frequency, current mode switching regulator. Current mode control provides fast transient response and excellent loop stability. New design techniques achieve high efficiency at high switching frequencies over a wide operating voltage range. A low dropout internal regulator maintains consistent performance over a wide range of inputs from 24V systems to Li-Ion batteries. An operating supply current of 1mA improves efficiency, especially at lower output currents. Shutdown reduces quiescent current to 15A. Maximum switch current remains constant at all duty cycles. Synchronization allows an external logic level signal to increase the internal oscillator into the range of 1.6MHz to 2MHz. Full cycle-by-cycle current control and thermal shutdown are provided. High frequency operation allows the reduction of input and output filtering components and permits the use of chip inductors.
APPLICATIO S
s s s s s
DSL Modems Portable Computers Regulated Wall Adapters Battery-Powered Systems Distributed Power
, LTC and LT are registered trademarks of Linear Technology Corporation. * Patent Pending
TYPICAL APPLICATIO
5V to 3.3V Step-Down Converter
CMDSH-3 0.18F INPUT 5V 2.2F CERAMIC
EFFICIENCY (%)
90
BOOST VIN LT1765-3.3 OFF ON SHDN SYNC FB GND VC 2.2nF VSW
1.5H
OUTPUT 3.3V 2.5A
UPS120
4.7F CERAMIC
1765 TA01
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Efficiency vs Load Current
VIN = 10V VOUT = 5V 85 80 75 70 0 1.0 1.5 0.5 SWITCH CURRENT (A) 2.0
1765 * TAO1a
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
ABSOLUTE
AXI U RATI GS
Input Voltage .......................................................... 25V BOOST Pin Above SW ............................................ 20V Max BOOST Pin Voltage .......................................... 35V SHDN Pin ............................................................... 25V FB Pin Current ....................................................... 1mA
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW BOOST 1 VIN 2 SW 3 GND 4 8 SYNC 7 VC 6 FB 5 SHDN
LT1765ES8
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125C, JA = 90C/W, JC(PIN 4) = 30C/W GROUND PIN CONNECTED TO LARGE COPPER AREA
S8 PART MARKING 1765
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER Maximum Switch Current Limit Oscillator Frequency Switch On Voltage Drop VIN Undervoltage Lockout VIN Supply Current Shutdown Supply Current Feedback Voltage VSHDN = 0V, VIN = 25V, VSW = 0V
q
CONDITIONS 3.3V < VIN < 25V I = 3A (Note 3)
q q q q
3V < VIN < 25V, 0.4V < VC < 0.9V (Note 3)
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(Note 1)
SYNC Pin Current .................................................. 1mA Operating Junction Temperature Range (Note 2) ........................................... - 40C to 125C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW GND BOOST VIN VIN SW SW NC GND 1 2 3 4 5 6 7 8 16 GND 15 NC 14 SYNC 13 VC 12 FB 11 SHDN 10 NC 9 GND
ORDER PART NUMBER LT1765EFE LT1765EFE-1.8 LT1765EFE-2.5 LT1765EFE-3.3 LT1765EFE-5 FE PART MARKING 1765EFE 1765EFE18 1765EFE25 1765EFE33 1765EFE-5
FE PACKAGE 16-LEAD PLASTIC TSSOP
JA = 45C/W, JC(PAD) = 10C/W EXPOSED PAD SOLDERED TO LARGE COPPER PLANE
MIN 3 1.1 2.47
TYP 4 1.25 270 2.6 1 15
MAX 6 1.6 430 2.73 1.3 35 55 1.218 1.224 1.836 2.55 3.366 5.1
UNITS A MHz mV V mA A A V V V V V V
LT1765 (Adj)
q
1.182 1.176 1.764 2.45 3.234 4.9
1.2 1.8 2.5 3.3 5
LT1765-1.8 LT1765-2.5 LT1765-3.3 LT1765-5
q q q q
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ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER FB Input Current FB Input Resistance CONDITIONS LT1765 (Adj) LT1765 LT1765-1.8 LT1765-3.3 LT1765-5 0.4V < VC < 0.9V IVC = 10A VFB = VNOM - 17% VFB = VNOM + 17% Duty Cycle = 0% VC = 1.2V, ISW = 800mA, VIN = 6V
q q q q q q q q q
MIN 10.5 14.7 19 29 150 500 80 70
TYP - 0.25 15 21 27.5 42 350 850 120 110 5 0.4 0.9
MAX - 0.5 21 30 39 60 1300 160 180
UNITS A k k k k Mho A A A/V V V % %
FB Error Amp Voltage Gain FB Error Amp Transconductance VC Pin Source Current VC Pin Sink Current VC Pin to Switch Current Transconductance VC Pin Minimum Switching Threshold VC Pin 3A ISW Threshold Maximum Switch Duty Cycle Minimum Boost Voltage Above Switch Boost Current SHDN Threshold Voltage SHDN Threshold Current Hysteresis SHDN Input Current (Shutting Down) SYNC Threshold Voltage SYNC Input Frequency SYNC Pin Resistance
85 80
90 1.8 20 70 2.7 30 140 1.40 10 - 13 2.2 2 20
ISW = 3A ISW = 1A (Note 4) ISW = 3A (Note 4)
q q q q q
V mA mA V A A V MHz k
1.27 4 -7 1.6
1.33 7 - 10 1.5
SHDN = 60mV Above Threshold
q
ISYNC = 1mA
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1765E is guaranteed to meet performance specifications from 0C to 125C. Specifications over the - 40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls.
Note 3: Minimum input voltage is defined as the voltage where the internal regulator enters lockout. Actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. See Applications Information. Note 4: Current flows into the BOOST pin only during the on period of the switch cycle.
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5 TYPICAL PERFOR A CE CHARACTERISTICS
FB vs Temperature (Adj)
1.220 1.215 350 300 TA = 125C
SWITCH VOLTAGE (mV)
1.210
1.205 1.200 1.195 1.190 1.185 1.180 -50 -25 0 25 50 75 100 125
FREQUENCY (MHz)
FB VOLTAGE (V)
TEMPERATURE (C)
1765 G01
SHDN Threshold vs Temperature
1.40 7 6 1.38
SHDN THRESHOLD (V)
1.36
VIN CURRENT (A)
1.34
1.32 1 1.30 -50 0 -25 0 25 50 75 TEMPERATURE (C) 100 125 0 5 10 15 VIN (V) 20 25 30
1765 G05
SHDN INPUT (A)
4
UW
Switch On Voltage Drop
1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 0 2 1 SWITCH CURRENT (A) 3
1765 G02
Oscillator Frequency
250 200 150 100 50 0 TA = 25C TA = -40C
1.10 -50
-25
0 25 50 75 TEMPERATURE (C)
100
125
1765 G03
SHDN Supply Current vs VIN
SHDN = 0V
5 4 3 2
1765 G04
SHDN IP Current vs Temperature
-12 -10 SHUTTING DOWN -8 -6 -4 -2 0 -50
STARTING UP
-25
0 25 50 75 TEMPERATURE (C)
100
125
1765 G06
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5 TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Input Voltage for 2.5V Out
3.5 300 VIN = 15V 3.3 INPUT VOLTAGE (V) VIN CURRENT (A) 250 200 150 100 50 0 1000 VIN CURRENT (A) 800 600 400 200 0 0 0.2 0.4 0.6 0.8 1 1.2 SHUTDOWN VOLTAGE (V) 1.4 0 5 10 15 20 INPUT VOLTAGE (V) 25 30
1765 G09
3.1
2.9
2.7
2.5 0.001
0.1 0.01 LOAD CURRENT (A)
Current Limit Foldback
4 40 3.0
SWITCH PEAK CURRENT (A)
SWITCH CURRENT 2 20
OUTPUT CURRENT (A)
3
1 FB CURRENT 0
0
0.2
0.4 0.6 0.8 FEEDBACK VOLTAGE (V)
OUTPUT CURRENT (A)
UW
1
1765 G07
SHDN Supply Current
1200
Input Supply Current
UNDERVOLTAGE LOCKOUT
1765 G08
Maximum Load Current, VOUT = 5V
2.8 30 L = 4.7H 2.6
FB INPUT CURRENT (A)
2.4
L = 2.2H
10
2.2 L = 1.5H
1
0 1.2
1765 G10
2.0 0 5 10 15 INPUT VOLTAGE (V) 20 25
1765 G11
Maximum Load Current, VOUT = 2.5V
3.0
L = 4.7H 2.8
L = 2.2H 2.6 L = 1.5H 2.4
2.2 0 5 10 15 INPUT VOLTAGE (V) 20 25
1765 G12
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
PI FU CTIO S
FB: The feedback pin is used to set output voltage using an external voltage divider (adjustable version) that generates 1.2V at the pin when connected to the desired output voltage. The fixed voltage 1.8V, 2.5V, 3.3V and 5V versions have the divider network included internally and the FB pin is connected directly to the output. If required, the current limit can be reduced during start up or shortcircuit when the FB pin is below 0.5V (see the Current Limit Foldback graph in the Typical Performance Characteristics section). An impedance of less than 5k on the adjustable version at the FB pin is needed for this feature to operate. BOOST: The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. VIN: This is the collector of the on-chip power NPN switch. This pin powers the internal circuitry and internal regulator. At NPN switch on and off, high di/dt edges occur on this pin. Keep the external bypass capacitor and catch diode close to this pin. All trace inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. Both VIN pins of the TSSOP package must be shorted together on the PC board. GND: The GND pin acts as the reference for the regulated output, so load regulation will suffer if the "ground" end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. Keep the path between the input bypass and the GND pin short. The exposed GND pad and/or GND pins of the package are directly attached to the internal tab. These pins/pad should be attached to a large copper area to reduce thermal resistance. VSW: The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the switch pin negative during switch off time. Negative voltage must be clamped with an external catch diode with a VBR <0.8V. Both VSW pins of the TSSOP package must be shorted together on the PC board. SYNC: The sync pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 20% and 80% duty cycle. The synchronizing range is from 1.6MHz to 2MHz. See Synchronization section in Applications Information for details. When not in use, this pin should be grounded. SHDN: The shutdown pin is used to turn off the regulator and to reduce input drain current to a few microamperes. The 1.33V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from operating until the input voltage has reached a predetermined level. Float or pull high to put the regulator in the operating mode. VC: The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally used for frequency compensation, but can do double duty as a current clamp or control loop override. This pin sits at about 0.4V for very light loads and 0.9V at maximum load. It can be driven to ground to shut off the output.
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BLOCK DIAGRA
The LT1765 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on. When switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low
INPUT
2.5V BIAS REGULATOR
SYNC
SHUTDOWN COMPARATOR
1.33V ERROR AMPLIFIER gm = 850Mho
SHDN 3A
INTERNAL VCC
VC
Figure 1. Block Diagram
-
+
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phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180 shift will occur. The current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. High switch efficiency is attained by using the BOOST pin to provide a voltage to the switch driver which is higher than the input voltage, allowing the switch to be saturated. This boosted voltage is generated with an external capacitor and diode. A comparator connected to the shutdown pin disables the internal regulator, reducing supply current.
0.005
+
INTERNAL VCC
-
CURRENT SENSE AMPLIFIER VOLTAGE GAIN = 40
SLOPE COMP
0.4V
BOOST
1.25MHz OSCILLATOR
S CURRENT COMPARATOR
RS FLIP-FLOP
DRIVER CIRCUITRY
+ -
7A
R
Q1 POWER SWITCH
PARASITIC DIODES DO NOT FORWARD BIAS
VSW
-
FB 1.2V GND
1765 F01
+
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
FB RESISTOR NETWORK
If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required, the respective fixed option part, -1.8, -2.5, -3.3 or -5, should be used. The FB pin is tied directly to the output; the necessary resistive divider is already included on the part. For other voltage outputs, the adjustable part should be used and an external resistor divider added. The suggested resistor (R2) from FB to ground is 10k. This reduces the contribution of FB input bias current to output voltage to less than 0.25%. The formula for the resistor (R1) from VOUT to FB is:
R1 = R2(VOUT - 1.2) 1.2 - R2(0.25A)
LT1765 (ADJ) ERROR AMPLIFIER VSW OUTPUT
+ -
1.2V FB R1
+
R2 10k
1765 F02
VC
GND
Figure 2. Feedback Network
INPUT CAPACITOR Step-down regulators draw current from the input supply in pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the voltage ripple at the input of LT1765 and to force the switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from:
IRIPPLE(RMS) = IOUT VOUT VIN - VOUT
(
) / VIN2
Ceramic capacitors are ideal for input bypassing. At higher switching frequency, the energy storage requirement of the input capacitor is reduced so values in the range of 1F to 4.7F are suitable for most applications. Their high frequency capacitive nature removes most ripple current
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rating and turn-on surge problems. Y5V or similar type ceramics can be used since the absolute value of capacitance is less important and has no significant effect on loop stability. If operation is required close to the minimum input required by the output or the LT1765, a larger value may be required. This is to prevent excessive ripple causing dips below the minimum operating voltage resulting in erratic operation. If tantalum capacitors are used, values in the 22F to 470F range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series tantalum capacitors are surge rated. AVX recommends derating capacitor operating voltage by 2:1 for high surge applications. OUTPUT CAPACITOR Unlike the input capacitor, RMS ripple current in the output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is triangular, with an RMS value given by: IRIPPLE(RMS) = 0.29(VOUT )(VIN - VOUT ) (L)( f)(VIN) The LT1765 will operate with both ceramic and tantalum output capacitors. Ceramic capacitors are generally chosen for their small size, very low ESR (effective series resistance), and good high frequency operation. Ceramic output capacitors in the 1F to 10F range, X7R or X5R type are recommended. Tantalum capacitors are usually chosen for their bulk capacitance properties, useful in high transient load applications. ESR rather than absolute value defines output ripple at 1.25MHz. Typical LT1765 applications require a tantalum capacitor with less than 0.3 ESR at 22F to 500F, see Table 2. This ESR provides a useful zero in the frequency response. Ceramic output capacitors with low ESR usually require a larger VC capacitor or an additional series R to compensate for this.
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
E Case Size AVX TPS, Sprague 593D AVX TAJ D Case Size AVX TPS, Sprague 593D C Case Size AVX TPS 0.2 (typ) 0.1 to 0.3 ESR (Max, ) 0.1 to 0.3 0.7 to 0.9
Table 2. Surface Mount Solid Tantalum Capacitor ESR and Ripple Current
Ripple Current (A) 0.7 to 1.1 0.4 0.7 to 1.1 0.5 (typ)
Figure 3 shows a comparison of output ripple for a ceramic and tantalum capacitor at 200mA ripple current.
VOUT USING 47F, 0.1 TANTALUM CAPACITOR (10mV/DIV) VOUT USING 2.2F CERAMIC CAPACITOR (10mV/DIV)
VSW (5V/DIV)
0.2s/DIV
Figure 3. Output Ripple Voltage Waveform
INDUCTOR CHOICE AND MAXIMUM OUTPUT CURRENT Maximum output current for an LT1765 buck converter is equal to the maximum switch rating (IP) minus one half peak to peak inductor ripple current. The LT1765 maintains a constant switch current rating at all duty cycles. (Patent Pending) For most applications, the output inductor will be in the 1H to 10H range. Lower values are chosen to reduce the physical size of the inductor, higher values allow higher output currents due to reduced peak to peak ripple current. The following formula gives maximum output current for continuous mode operation, implying that the peak to peak ripple (2x the term on the right) is less than the maximum switch current.
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IOUT (MAX) = Continuous Mode
IP - (VOUT )(VIN - VOUT ) 2(L)(f)(VIN )
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For VIN = 8V, VOUT = 5V and L = 3.3H, IOUT (MAX) = 3 -
2 3.3 * 10- 6 1.25 * 106 8
= 3 - 0.23 = 2.77A
(
(5)(8 - 5)
)(
)( )
Note that the worst case (minimum output current available) condition is at the maximum input voltage. For the same circuit at 15V, maximum output current would be only 2.6A. Inductor Selection The output inductor should have a saturation current rating greater than the peak inductor current set by the current comparator of the LT1765. The peak inductor current will depend on the output current, input and output voltages and the inductor value: IPEAK = IOUT + VOUT (VIN - VOUT ) 2(L)( f)(VIN )
1765 F03
VIN = Maximum input voltage f = Switching frequency, 1.25MHz If an inductor with a peak current lower than the maximum switch current of the LT1765 is chosen a soft-start circuit in Figure 10 should be used. Also, short-circuit conditions should not be allowed because the inductor may saturate resulting in excessive power dissipation. Also, consideration should be given to the resistance of the inductor. Inductor conduction loses are directly proportional to the DC resistance of inductor. Sometime, the manufacturers will also provide maximum current rating based on the allowable losses in the inductor. Care should be taken, however. At high input voltages and low DCR, excessive switch current could flow during shorted output condition. Suitable inductors are available from Coilcraft, Coiltronics, Dale, Sumida, Toko, Murata, Panasonic and other manufacturers.
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
Table 3
PART NUMBER Coiltcraft DO1608C-222 Sumida CDRH3D16-1R5 CDRH4D18-1R0 CDC5D23-2R2 CR43-1R4 CDRH5D28-2R6 Toko (D62F)847FY-2R4M (D73LF)817FY-2R2M VALUE (H) 2.2 1.5 1.0 2.2 1.4 2.6 2.4 2.2 IRMS (Amps) 2.4 1.6 1.7 2.2 2.5 2.6 2.5 2.7 DCR () 0.07 0.043 0.035 0.03 0.056 0.013 0.037 0.03
CATCH DIODE The diode D1 conducts current only during switch off time. Peak reverse voltage is equal to regulator input voltage. Average forward current in normal operation can be calculated from:
ID ( AVG) =
IOUT VIN - VOUT VIN
(
)
The only reason to consider a larger than 3A diode is the worst-case condition of a high input voltage and shorted output. With a shorted condition, diode current will increase to a typical value of 4A, determined by peak switch current limit of the LT1765. A higher forward voltage will also limit switch current. This is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions must be tolerated. BOOST PIN For most applications, the boost components are a 0.18F capacitor and a CMDSH-3 diode. The anode is typically connected to the regulated output voltage to generate a voltage approximately VOUT above VIN to drive the output stage. The output driver requires at least 2.7V of headroom throughout the on period to keep the switch fully saturated. However, the output stage discharges the boost capacitor during this on time. If the output voltage is less than 3.3V, it is recommended that an alternate boost
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HEIGHT (mm) 2.9 1.8 2.0 2.5 3.5 3.0 2.7 3.0
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supply is used. The boost diode can be connected to the input, although, care must be taken to prevent the 2x VIN boost voltage from exceeding the BOOST pin absolute maximum rating. The additional voltage across the switch driver also increases power loss, reducing efficiency. If available, an independent supply can be used with a local bypass capacitor. A 0.18F boost capacitor is recommended for most applications. Almost any type of film or ceramic capacitor is suitable, but the ESR should be <1 to ensure it can be fully recharged during the off time of the switch. The capacitor value is derived from worst-case conditions of 700ns on-time, 90mA boost current, and 0.7V discharge ripple. This value is then guard banded by 2x for secondary factors such as capacitor tolerance, ESR and temperature effects. The boost capacitor value could be reduced under less demanding conditions, but this will not improve circuit operation or efficiency. Under low input voltage and low load conditions, a higher value capacitor will reduce discharge ripple and improve start up operation. SHUTDOWN AND UNDERVOLTAGE LOCKOUT Figure 4 shows how to add undervoltage lockout (UVLO) to the LT1765. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur.
LT1765 INPUT R1 IN 3A 7A 1.33V VCC VSW
SHDN C1 R2 GND
+
OUTPUT
1765 F04
Figure 4. Undervoltage Lockout
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
An internal comparator will force the part into shutdown below the minimum VIN of 2.6V. This feature can be used to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the shutdown pin can be used. The threshold voltage of the shutdown pin comparator is 1.33V. A 3A internal current source defaults the open pin condition to be operating (see Typical Performance Graphs). Current hysteresis is added above the SHDN threshold. This can be used to set voltage hysteresis of the UVLO using the following:
R1 = R2 =
VH - VL 7A 1.33V (VH - 1.33V) + 3A R1
VH - Turn-on threshold VL - Turn-off threshold Example: switching should not start until the input is above 4.75V and is to stop if the input falls below 3.75V. VH = 4.75V VL = 3.75V
4.75V - 3.75V = 143k 7A 1.33V = 49.4k R2 = (4.75V - 1.33V) + 3A 143k R1 =
Keep the connections from the resistors to the SHDN pin short and make sure that the interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the SHDN pin should be bypassed with a 1nF capacitor to prevent coupling problems from the switch node. SYNCHRONIZATION The SYNC pin is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 20% and 80%. The
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input can be driven directly from a logic level output. The synchronizing range is equal to initial operating frequency up to 2MHz. This means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (1.6MHz), not the typical operating frequency of 1.25MHz. Caution should be used when synchronizing above 1.8MHz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. LAYOUT CONSIDERATIONS As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 5, must be kept as short as possible. Shortening this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT1765 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT1765 that may exceed its absolute
LT1765 VIN SW L1 5V VIN C3 HIGH FREQUENCY CIRCULATING PATH D1 C1 LOAD
1765 F05
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Figure 5. High Speed Switching Path
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO U
MINIMIZE D1, C3 LT1765 LOOP VIN GND C3 D2 CC KEEP FB AND VC COMPONENTS AND TRACES AWAY FROM HIGH FREQUENCY, HIGH INPUT COMPONENTS C2
INPUT 15V
C3 4.7F CERAMIC VIN
C2 0.18F BOOST VSW LT1765-33 FB GND VC CC 2.2nF
OFF ON
SHDN SYNC
Figure 6. Typical Application and Layout (Topside Only Shown)
maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The VC and FB components should be kept as far away as possible from the switch and boost nodes. The LT1765 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. Board layout also has a significant effect on thermal resistance. The exposed pad or GND pin is a continuous copper plate that runs under the LT1765 die. This is the best thermal path for heat out of the package as can be seen by the low JC of the exposed pad package. Reducing the thermal resistance from Pin 4 or exposed pad onto the board will reduce die temperature and increase the power capability of the LT1765. This is achieved by providing as much copper area as possible around this pin/pad. Also, having multiple solder filled feedthroughs to a continuous copper plane under LT1765 will help in reducing thermal resistance. Ground plane is usually suitable for this purpose. In multilayer PCB designs, placing a ground plane next to the layer with the LT1765 will reduce thermal resistance to a minimum.
12
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D2 CMDSH-3
L1 2.7H
OUTPUT 3.3V 2.5A
L1 D1
D1 B220A
C1 4.7F CERAMIC
1765 F06
VOUT C1 KELVIN SENSE VOUT
GND
PLACE FEEDTHROUGHS UNDER AND AROUND GROUND PAD FOR GOOD THERMAL CONDUCTIVITY
1765 F6a
THERMAL CALCULATIONS Power dissipation in the LT1765 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. Switch loss:
RSW (IOUT ) (VOUT ) PSW = + 17ns(IOUT )(VIN)( f) VIN Boost current loss for VBOOST = VOUT:
2
VOUT 2 (IOUT / 50) PBOOST = VIN Quiescent current loss:
PQ = VIN 0.001
(
)
RSW = Switch resistance ( 0.13 at hot) 17ns = Equivalent switch current/voltage overlap time f = Switch frequency
sn1765 1765fas
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
(0.13)(2)2 (5) + =
Example: with VIN = 10V, VOUT = 5V and IOUT = 2A:
PSW 17 * 10-9 (2)(10) 1.25 * 106 10 = 0.26 + 0.43 = 0.69W
(
)
(
PBOOST
10 PQ = 10(0.001) = 0.01W
(5)2 (2 / 50) = 0.1W =
Total power dissipation, PTOT, is 0.69 + 0.1 + 0.01 = 0.8W. Thermal resistance for the LT1765 16-lead TSSOP exposed pad package is influenced by the presence of internal or backside planes. With a full plane under the package, thermal resistance will be about 45C/W. With no plane under the package, thermal resistance will increase to about 110C/W. For the exposed pad package JC(PAD) = 10C/W. Thermal resistance is dominated by board performance. To calculate die temperature, use the appropriate thermal resistance number and add in worstcase ambient temperature: TJ = TA + JA (PTOT) When estimating ambient, remember the nearby catch diode will also be dissipating power.
PDIODE =
(VF )(VIN - VOUT )(ILOAD )
VIN
VF = Forward voltage of diode (assume 0.5V at 2A)
PDIODE =
(0.5)(10 - 5)(2) = 0.5W
10
500k GND VC
TJ = TA + JA(PTOT) + B(PDIODE) TJ = 25 + 45 (0.8) + 35 (0.5) = 79C
RC CC
CF
1765 F07
Figure 7. Model for Loop Response
sn1765 1765fas
+
Typical thermal resistance of the board B is 35C/W. At an ambient temperature of 25C,
gm = 850mho 1.2V
-
Notice that the catch diode's forward voltage contributes a significant loss in the overall system efficiency. A larger, lower VF diode can improve efficiency by several percent.
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DIE TEMPERATURE MEASUREMENT
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)
If a true die temperature is required, a measurement of the SYNC to GND pin resistance can be used. The SYNC pin resistance across temperature must first be calibrated, with no significant output load, in an oven. An initial value of 40k with a temperature coefficient of 0.16%/C is typical. The same measurement can then be used in operation to indicate the die temperature. FREQUENCY COMPENSATION Before starting on the theoretical analysis of frequency response, the following should be remembered--the worse the board layout, the more difficult the circuit will be to stabilize. This is true of almost all high frequency analog circuits, read the `LAYOUT CONSIDERATIONS' section first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or catch diode, and connecting the VC compensation to a ground track carrying significant switch current. In addition, the theoretical analysis considers only first order ideal component behavior. For these reasons, it is important that a final stability check is made with production layout and components. The LT1765 uses current mode control. This alleviates many of the phase shift problems associated with the inductor. The basic regulator loop is shown in Figure 7, with both tantalum and ceramic capacitor equivalent circuits. The LT1765 can be considered as two gm blocks, the error amplifier and the power stage.
LT1765 CURRENT MODE POWER STAGE gm = 5mho VSW ERROR AMPLIFIER FB R1 TANTALUM CERAMIC ESR ESL C1 OUTPUT
+
C1 R2
13
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
Figure 8 shows the overall loop response with a 330pF VC capacitor and a typical 100F tantalum output capacitor. The response is set by the following terms:
Error amplifier: DC gain set by gm and RL = 850 * 500k = 425. Pole set by CF and RL = (2 * 500k * 330p)-1 = 965Hz. Unity-gain set by CF and gm = (2 * 330p * 850-1)-1 = 410kHz. Power stage: DC gain set by gm and RL (assume 5) = 5 * 5 = 25. Pole set by COUT and RL = (2 * 100 * 10)-1 = 159Hz. Unity-gain set by COUT and gm = (2 * 100 * 5-1)-1 = 8kHz. Tantalum output capacitor: Zero set by COUT and CESR = (2 * 100 * 0.1)-1 = 15.9kHz.
The zero produced by the ESR of the tantalum output capacitor is very useful in maintaining stability. Ceramic output capacitors do not have a zero due to very low ESR, but are dominated by their ESL. They form a notch in the 1MHz to 10MHz range. Without this zero, the VC pole must be made dominant. A typical value of 2.2nF will achieve this. If better transient response is required, a zero can be added to the loop using a resistor (RC) in series with the compensation capacitor. As the value of RC is increased, transient response will generally improve, but two effects limit its value. First, the combination of output capacitor ESR and a large RC may stop loop gain rolling off altogether. Second, if the loop gain is not rolled suffi80 60 40
GAIN (dB)
VOUT = 5V COUT = 100F, 0.1 CC = 330pF RC/CF = 0 ILOAD = 1A PHASE
180 150 120 90 60
20 0
GAIN -20 -40 30 0 1M
1765 F08
10
100
1k 10k FREQUENCY (Hz)
100k
Figure 8. Overall Loop Response
sn1765 1765fas
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ciently at the switching frequency, output ripple will perturb the VC pin enough to cause unstable duty cycle switching similar to subharmonic oscillation. This may not be apparent at the output. Small signal analysis will not show this since a continuous time system is assumed. If needed, an additional capacitor (CF) can be added to the VC pin to form a pole at typically one fifth the switching frequency (If RC = ~ 5k, CF = ~ 100pF) When checking loop stability, the circuit should be operated over the application's full voltage, current and temperature range. Any transient loads should be applied and the output voltage monitored for a well-damped behavior. CONVERTER WITH BACKUP OUTPUT REGULATOR In systems with a primary and backup supply, for example, a battery powered device with a wall adapter input, the output of the LT1765 can be held up by the backup supply with its input disconnected. In this condition, the SW pin will source current into the VIN pin. If the SHDN pin is held at ground, only the shutdown current of 6A will be pulled via the SW pin from the second supply. With the SHDN pin floating, the LT1765 will consume its quiescent operating current of 1mA. The VIN pin will also source current to any other components connected to the input line. If this load is greater than 10mA or the input could be shorted to ground, a series Schottky diode must be added, as shown in Figure 9. With these safeguards, the output can be held at voltages up to the VIN absolute maximum rating. BUCK CONVERTER WITH ADJUSTABLE SOFT-START Large capacitive loads or high input voltages can cause high input currents at start-up. Figure 10 shows a circuit that limits the dv/dt of the output at start-up, controlling the capacitor charge rate. The buck converter is a typical configuration with the addition of R3, R4, CSS and Q1. As the output starts to rise, Q1 turns on, regulating switch current via the VC pin to maintain a constant dv/dt at the output. Output rise time is controlled by the current through CSS defined by R4 and Q1's VBE. Once the output is in regulation, Q1 turns off and the circuit operates normally. R3 is transient protection for the base of Q1.
PHASE (DEG)
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LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
MBRS330T3* REMOVABLE INPUT
VIN 83k LT1765-3.3 SHDN SYNC GND 28.5k 2.2F
* ONLY REQUIRED IF ADDITIONAL LOADS ON THE INPUT CAN SINK >10mA
Figure 9. Dual Source Supply with 6A Reverse Leakage
D2 CMDSH-3 C2 0.18F INPUT 12V C3 2.2F BOOST VIN VSW LT1765-5 SHDN FB SYNC GND VC D1 C1 100F
L1 5H
+
CC 330pF
Q1
CSS R3 15nF 2k
1765 F10
R4 47k
D1: UPS120 Q1: 2N3904
Figure 10. Buck Converter with Adjustable Soft Start
RiseTime =
(R4)(C SS )(VOUT ) (VBE )
Using the values shown in Figure 10,
(47 * 103 )(15 * 10-9 )(5) = 5ms 0.7 The ramp is linear and rise times in the order of 100ms are possible. Since the circuit is voltage controlled, the ramp rate is unaffected by load characteristics and maximum output current is unchanged. Variants of this circuit can be used for sequencing multiple regulator outputs. RiseTime =
U
CMDSH-3 0.18F BOOST VSW FB VC 2.2nF UPS120 4.7F 5H 3.3V, 2A ALTERNATE SUPPLY
1765 F09
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Dual Output Converter The circuit in Figure 11 generates both positive and negative 5V outputs with a single piece of magnetics. The two inductors shown are actually just two windings on a standard B H Electronics inductor. The topology for the 5V output is a standard buck converter. The - 5V topology would be a simple flyback winding coupled to the buck converter if C4 were not present. C4 creates a SEPIC (single-ended primary inductance converter) topology which improves regulation and reduces ripple current in L1. Without C4, the voltage swing on L1B compared to L1A would vary due to relative loading and coupling losses. C4 provides a low impedance path to maintain an equal voltage swing in L1B, improving regulation. In a flyback converter, during switch on time, all the converter's energy is stored in L1A only, since no current flows in L1B. At switch off, energy is transferred by magnetic coupling into L1B, powering the - 5V rail. C4 pulls L1B positive during switch on time, causing current to flow, and energy to build in L1B and C4. At switch off, the energy stored in both L1B and C4 supply the -5V rail. This reduces the current in L1A and changes L1B current waveform from square to triangular. For details on this circuit, including maximum output currents, see Design Note 100.
OUTPUT 5V 1A
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15
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO U
D2 CMDSH-3 C2 0.18F INPUT 12V BOOST VIN LT1765-5 SHDN SYNC GND C3 2.2F 25V CERAMIC GND RC 3.3k CC 4700pF C4 4.7F 16V CERAMIC * L1 IS A SINGLE CORE WITH TWO WINDINGS COILTRONICS CTX5-1A IF LOAD CAN GO TO ZERO, AN OPTIONAL PRELOAD OF 1k TO 5k MAY BE USED TO IMPROVE LOAD REGULATION D1, D3: B220A FB VC 4.7F 6.3V CERAMIC D1 VSW L1A* OUTPUT 5V AT 1.5A 4.7F 6.3V L1B* CERAMIC OUTPUT -5V AT 1.1A D3
1765 F11a
MAX -5V LOAD (mA)
16
W
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Figure 11a. Dual Output Converter
Max Negative Load vs Positive Load
1200 1000 800 600 400 200 0 10 100 1000 5V LOAD CURRENT (mA) 10000
1765 F11b
Figure 11b. Dual Output Converter (Output Currents)
sn1765 1765fas
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
APPLICATIO S I FOR ATIO
INPUT 5V
VIN
VSW U1 SYNC LT1765-5 FB SHDN VC GND CC 1800pF RC 2.4k
C3 2.2F 16V X5R CERAMIC
L1: CDRH6D28-3R0
Figure 12. Positive-to-Negative Low Output Ripple Converter
VIN
VSW U1 SYNC LT1765FE FB SHDN VC GND CC 4700pF RC 6.8k
C3 22F 16V X5R CERAMIC OUTPUT -9V AT 1A
L1: CDRH5D28-2R5 BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 13. Negative Boost Converter
U
D2 CMDSH-3 C2 0.22F BOOST L1 3H D1 B220A C1 10F 6.3V X5R CERAMIC CF 100pF OUTPUT -5V AT 1A
1765 F12
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D2 CMDSH-3 C2 0.22F BOOST
INPUT -5V
L1 2.5H
D1 UPS120 R2 10k R1 64.9k
C1 2.2F 6.3V X5R
CF 100pF
1765 F13
sn1765 1765fas
17
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
PACKAGE DESCRIPTIO
6.60 0.10 4.50 0.10 0.45 0.05 1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD 4.30 - 4.48* (.169 - .176)
0.105 - 0.180 (.0041 - .0071)
0.50 - 0.70 (.020 - .028)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
18
U
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663, Exposed Pad Variation BB)
4.95 - 5.05* (.196 - .204) 3.8 (.149) 16 1514 13 12 1110 9 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 3.0 (.118) 6.25 - 6.50 (.246 - .256) 12345678 1.15 (.0453) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) 0.05 - 0.15 (.002 - .006)
FE16 TSSOP 1101
sn1765 1765fas
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
PACKAGE DESCRIPTIO U
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP 2 3 4 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 0.050 (1.270) BSC
SO8 1298
0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 (0.406 - 1.270)
sn1765 1765fas
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1765/LT1765-1.8/LT1765-2.5/ LT1765-3.3/LT1765-5
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PART NUMBER LT1370 LT1371 LT1372/LT1377 LT1374 LT1375/LT1376 LT1507 LT1576 LT1578 LT1616 LT1676/LT1776 LTC1735 LT1767 LTC1877 LTC1878 DESCRIPTION High Efficiency DC/DC Converter High Efficiency DC/DC Converter 500kHz and 1MHz High Efficiency 1.5A Switching Regulators High Efficiency Step-Down Switching Regulator 1.5A Step-Down Switching Regulators 1.5A Step-Down Switching Regulator 1.5A Step-Down Switching Regulator 1.5A Step-Down Switching Regulator 600mA Step-Down Switching Regulator Wide Input Range Step-Down Switching Regulators High Efficiency Synchronous Step-Down, N-Ch Drive 1.5A Step-Down Switching Regulator High Efficiency Monolithic Step-Down Regulator High Efficiency Monolithic Step-Down Regulator COMMENTS 42V, 6A, 500kHz Switch 35V, 3A, 500kHz Switch Boost Topology 25V, 4.5A, 500kHz Switch 500kHz, Synchronizable in SO-8 Package 500kHz, 4V to 16V Input, SO-8 Package 200kHz, Reduced EMI Generation 200kHz, Reduced EMI Generation 1.4MHz, 4V to 25V Input, ThinSOTTM Package 60V Input, 700mA Internal Switches, N8, S8 Burst Mode(R) Operation, 16-Pin Narrow SSOP 200kHz, VIN = 5.5V to 60V, SSOP-16, TSSOP-16E 1.25MHz, 1.5A, 25V Input, MS8 Package 550kHz, MS8, VIN Up to 10V, IQ =10A, IOUT to 600mA at VIN = 5V 550kHz, MS8, VIN Up to 6V, IQ = 10A, IOUT to 600mA at VIN = 3.3V 500kHz, VIN = 5.5V to 60V, Adjustable Fixed 5V, SSOP-16, TSSOP-16E VIN = 0.5V to 5V, Up to 97% Efficiency Synchronizable Oscillator from 100kHz to 3MHz, MS10 VIN = 0.7V to 5V, Up to 95% Efficiency Synchronizable Oscillator from 100kHz to 3MHz, MS10 Up to 95% Efficiency, 100% Duty Cycle, IQ = 10A, VIN = 2.65V to 6V, MS8
LT1766/LT1766-5 Wide Input Range, 1.5A, Step-Down Regulator
LT1956/LT1956-5 Wide Input Range, 1.5A, Step-Down Regulator LTC3401 LTC3402 LTC3404 Single Cell, High Current (1A), Micropower, Synchronous 3MHz Step-Up DC/DC Converter Single Cell, High Current (2A), Micropower, Synchronous 3MHz Step-Up DC/DC Converter 1.4MHz High Efficiency, Monolithic Synchronous Step-Down Regulator
Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
sn1765 1765fas
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 0802 1.5K REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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